SDP on Full Stack VLSI Design


SDP on “Full Stack VLSI Design”
Event Name
EVENT NAME SDP on “Full Stack VLSI Design”
Event Description

The Department of Electronics and Computer Science, SAKEC, in collaboration with SAKEC IIC 5.0 is organizing

SDP on Full Stack VLSI Design”

Want to be a successful VLSI Designer
Want to take a step further in the industry of VLSI design?
Need to standout in this world of competition?
Then look no further than this event……
This event would help you to
Gain strong knowledge about VLSI Design and you will shine out with flying colours for VLSI Industry.
Receive guidance from the leading industry professionals from the field of VLSI Design.

Date of Sessions :
30th January 2023.
Time: 10:30am onwards.

Workshop Registration Fees:- Nil

Venue :
7th Floor Auditorium

If any Query, please contact
Convener- Dr. Subha Subramaniam(HOD)- 9967013504

Staff Co-ordinators :
Nibha Desai – 9320210378
Aparajita Bera – 9833748985

Student Co-ordinators :
Satyam Jagdale: 8369656113
Amar Chouhan: 8369164805
Geetanjali Sahoo: 9137961796

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