EXTC STTP VLSI 2018

Advanced VLSI Design and Applications with hands-on in CADENCE toolset
STTP 2018
Event Description Department of Electronics & Telecommunication Engineering, SAKEC is organizing IETE approved One week STTP On “Advanced VLSI Design and Applications with hands-on in CADENCE toolset”. The main objective of this program is to provide Hands-On experience in VLSI Design on CADENCE tool .
Date & Time 25th June 2018 to 30th June 2018, 9.30 AM to 5.00 PM
Who Can Attend?

Students/ Faculty members / Professionals working in the field of Electronics and Telecommunication, Electronics Engineering Colleges, Technical Institutes, Research Scholars.

Course Contents: Course covers the following Topics:

  1. 3-days exclusive Hands-on sessions on CADENCE tool
  2. RF CMOS VLSI
  3. Data Converters
  4. Verification
  5. System Design using FPGA
  6. Full Custom Design
  7. ASIC Design
  8. Applications of VLSI
STTP Convenor Ms. T. P. VINUTHA
I/c HOD,
Department of Electronics & Telecommunication Engineering
STTP Coordinator Shridhar R. Sahu: Mob: 9969988751
Email Id: shridhar.sahu@sakec.ac.in
Course Fees
Participant Fees
Faculty members / Industry Members 3000
Research Scholars/ Students 1000
Brochure

Click here to download the Brochure

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